Today, typical display devices used for information display and the like include CRTs, liquid crystal display devices, and EL display devices. Conventionally, CRTs have been widely used as display devices in terms of relatively low device cost and high display quality. However, it is difficult to miniaturize Braun tubes and achieve low power consumption. In view of this, there has been an increasing demand for liquid crystal display devices and EL display devices recently. Further, IC tags capable of reading and writing data in a non-contact manner are expected to create a large market in the use of distribution and personal information management. Such IC tags include a large number of arithmetic devices embedded therein.
On the other hand, general active elements used for display devices and arithmetic devices are made of transistors having a semiconductor material, a first electrode (gate electrode 100), a second electrode (source electrode 101), and a third electrode (drain electrode 102). Examples of a general structure of a transistor include a planar type (refer to FIG. 21-(a)) and an inverse stagger type (refer to FIG. 21-(b)).
Regarding semiconductor materials, in recent years, organic semiconductor materials to which a coating process can be applied have been actively developed. Organic semiconductor devices that can be manufactured through coating require no vacuum film forming process, so that it is possible to substantially reduce a manufacturing cost.
In recent years, polythiophene materials have attracted attention as organic semiconductor materials with large mobility, to which the coating process can be applied (refer to Non-patent Document 1). However, the mobility is less than 0.1 cm2/V·s and is about ten times smaller in comparison with mobility of amorphous silicon. In accordance with this, in general, transistors in which organic semiconductor materials are used have kHz order of cutoff frequency as an index of high speed responsiveness. Thus, it is impossible to use such transistors for driving high-definition movie display devices that require not less than several MHz order of cutoff frequency or for IC tags.
In addition to an increase of the mobility of organic semiconductor materials, a reduction of a channel length 104 of a transistor may be employed as a way of improving the cutoff frequency. However, in order to perform patterning on the source electrode 101 and the drain electrode 102 in a channel length of about 1 μm or less, complicated steps and expensive manufacturing apparatus are necessary in general, so that this is problematic in that the manufacturing cost is increased.
In order to solve such problems, a SIT structure (refer to FIG. 22-(a)) is known in which the source electrode 101, the gate electrode 100, and the drain electrode 102 are successively laminated. In the SIT structure, a current between the source electrode 101 and the drain electrode 102 is ON/OFF through control as shown in FIG. 22-(b), in which by applying a gate voltage 6, depletion layers 107 in a semiconductor layer 105 are increased and resistance between the source electrode 101 and the drain electrode 102 is increased.
As understood from FIG. 22-(a), it is possible to control the channel length 109 of the SIT structure in accordance with a film thickness of the semiconductor layer 105. A manufacturing process of the SIT structure is very easy in terms of a reduced channel length, so that the SIT structure is expected to be a transistor with high speed responsiveness. However, the SIT structure is problematic in that the depletion layers 107 are not spread in an entire area in a direction 108 of a channel width thereof when a space between the gate electrodes 100 is increased and the current is increased when the current is OFF. In view of this, it is necessary to perform patterning such that the space between the gate electrodes 100 is less than 1 μm, so that complicated steps are necessary for the manufacturing process.
Further, a parasitic capacity in an inside of an element must be reduced in order to improve the cutoff frequency.
For example, in the case of FIG. 21-(a), the parasitic capacity is formed by holding a gate insulating film 103 between the gate electrode 100 and the source electrode 101 and between the gate electrode 100 and the drain electrode 102. If the parasitic capacity is large, portions irrelevant to circuit operations are charged by the application of the gate voltage, so that high-speed response is difficult. Moreover, if the gate voltage has a high frequency, impedance of a capacitor is substantially small, so that the gate voltage is flown to the source electrode 101 and the drain electrode 102. As a result, power consumption of the element becomes vary large, and it is difficult to apply the element to an application in which a battery is used for driving as in mobile use, for example.
In accordance with this, in the planar type, it is necessary to align the gate electrode 100, the source electrode 101, and the drain electrode 102 such that they are hardly overlapped with one another. In particular, when a material of the substrate is subject to shrinkage such as a resin film, the alignment becomes more difficult as an area is increased.
In the SIT structure, the parasitic capacity is formed by holding the semiconductor layer 105 using the gate electrode 100, the source electrode 101, and the drain electrode 102 in the same manner as shown in FIG. 22-(a), so that failure may be generated in performing high-speed operations or achieving low power consumption. Moreover, it is very difficult to align the source electrode 101 and drain electrode 102 such that they are not overlapped with the microfabricated gate element.
In view of this, Patent Document 1 discloses a field-effect transistor including: a first electrode formed on a substrate and having a convex portion; an insulating layer covering the first electrode; a second electrode formed on the insulating layer and positioned above the convex portion of the first electrode; a third electrode disposed on at least one of both sides of the convex portion of the first electrode via the insulating layer and positioned lower than the convex portion of the first electrode; and a semiconductor layer in contact with the second electrode and the third electrode while being separated from the first electrode using the insulating layer.
In addition, Patent Document 2 discloses a field-effect transistor including: (A) a gate electrode formed on a substrate and having a top face, a first side and a second side where a form of a cross-section is substantially a quadrangular shape; (B) an insulating film formed on the top face, the first side, and the second side of the gate electrode; (C) a first source/drain electrode formed on a portion of the insulating film positioned on the top face of the gate electrode; (D) a second source/drain electrode formed on a portion of the substrate facing the first side of the gate electrode; (E) a third source/drain electrode formed on a portion of the substrate facing the second side of the gate electrode; and (F) a semiconductor material layer formed from the second source/drain electrode to the third source/drain electrode via the first source/drain electrode. In the field-effect transistor, a first field-effect transistor is constructed with the gate electrode, the first source/drain electrode, a first channel forming area made of a portion of the semiconductor material layer formed on the portion of the insulating layer positioned on the first side of the gate electrode, and the second source/drain electrode and a second field-effect transistor is constructed with the gate electrode, the first source/drain electrode, a second channel forming area made of a portion of the semiconductor material layer formed on the portion of the insulating layer positioned on the second side of the gate electrode, and the third source/drain electrode.
However, in the above-mentioned structures, the parasitic capacity is formed between the gate electrode and the source electrode or the drain electrode, so that high-speed response is difficult.    Patent Document 1: Japanese Laid-Open Patent Application No. 2005-19446    Patent Document 2: Japanese Laid-Open Patent Application No. 2004-349292    Non-patent Document 1: Applied Physics Letter, vol. 69, pp. 4108 (1996)